Assertion

Verification

The Assertion block monitors a signal at every simulation step and checks whether it satisfies a user-defined property. When the condition holds the output port emits 1; when it is violated the output emits 0 and a violation is recorded with its timestamp. The block body turns green on pass and red on failure, giving immediate visual feedback during simulation.

Use the Assertion block to encode safety constraints and design requirements directly in a diagram — for example, to verify that a control signal never saturates, that a physical quantity stays within safe bounds, or that two signals remain in a valid relationship. Assertions act as lightweight runtime monitors without requiring external test scripts.

Mathematical Model

\text{assert}(f(u(t)))

Inputs & Outputs

Direction	ID	Label	Type	Status
→ In	`in`	Signal	number	Required
← Out	`status`	Pass	number	Output

Parameters

Parameters	Label	Type	Default	Description
`mode`	Condition	select	`between`	Which property to check
`lowerBound`	Lower Bound	number	`-1`	Lower bound of the assertion range
`upperBound`	Upper Bound	number	`1`	Upper bound of the assertion range

Usage Examples

Verifying actuator signal stays within saturation limits

Controller → Assertion → Actuator
             mode=between  lowerBound=-10  upperBound=10

The status output can be plotted alongside the signal to log every violation instant.

Detecting when a temperature leaves a safe range

TempSensor → Assertion → Display
              mode=between  lowerBound=15  upperBound=85

Confirming a signal is strictly positive

PressureSensor → Assertion → FlowCalc
                  mode=above  lowerBound=0

Remarks & Best Practices

Pass-through signal: The input signal is not modified. Connect the original signal line to downstream blocks and use the status output only for monitoring or conditional logic.
Status output: The status port outputs a numeric 1 (pass) or 0 (fail) at each step; it can be fed into a Scope or used to gate other logic.
Disconnected input: If the input port is unconnected, the block treats the signal as zero and evaluates the condition against zero each step.
Bounds and mode interaction: lowerBound is ignored when mode=below; upperBound is ignored when mode=above. Set the irrelevant bound to any value — it has no effect.
Logging violations: Violations are recorded with timestamps in the simulation log. Review the log after a run to identify all failure windows.
Not a hard stop: By default an assertion violation does not halt the simulation; it only flags the condition. Combine with a Stop block downstream of the status port if a hard stop is required.

Related Components

uPlotDisplay: Plot the status output over time to visualise the violation timeline.
Comparator: Performs a single numeric comparison and outputs a boolean signal; use when you need the comparison result as a signal rather than as a monitored property.
Switch: Can use the Assertion status output to switch between signal paths in response to a constraint violation.