Discrete

UnitDelay Block

Delays input signal by one sample period (z⁻¹ operator)

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# Unit Delay Block

Description

Delays the input signal by exactly one sample period (z⁻¹ operator). This is the fundamental building block for discrete-time systems, digital filters, and state machines.

Mathematical Model

y[n] = u[n-1] y[0] = initialCondition

Parameters

initialCondition

The output value at the first simulation step before any input has been received.

Remarks

See Also